A1SI Engineering Services · Hardware
A1SI picks up hardware programs at any stage and drives them to a production hand-off: block diagram, schematic, PCB layout, prototype bring-up, EMC pre-compliance, and DFM-cleaned files for the contract manufacturer. We work at the bench every day — Altium and LTspice on the desktop, a Saleae and a Tektronix scope at the elbow, a test fixture wired to the panel that's about to enter production. The engineering posture comes from 30+ years of shipping production-floor controllers (Ford FN-145 seat testers, the DVP2 digital multi-printer, the Spartan ActiveRide suspension controller); every board we ship is designed to be testable, repairable, and respinnable in vendor-neutral file formats.
Capabilities
Every hardware program touches the same six disciplines in some combination. A1SI runs all of them in-house, with the people who own the schematic also running the bring-up and the EMC pre-compliance scan — no hand-offs across walls, no "another team owns that signal."
Op-amp and instrumentation-amplifier stages, precision references, ADC / DAC interfaces, sensor front-ends. Ground-loop discipline, current-return-path planning, anti-aliasing filters specified against the converter datasheet. PSpice and LTspice models on every non-trivial loop before layout.
MCU and SoC integration, FPGA bring-up, DDR3 / DDR4 memory, USB 2.0 / 3.0, Gigabit Ethernet, PCIe Gen 1 / 2, MIPI CSI/DSI. Controlled-impedance stack-ups, length-matched buses, eye-diagram analysis where the margin is real.
2-layer prototypes through 16+ layer controlled-impedance production boards. Mixed analog / RF / digital partitioning, plane-stitching strategy, design-for-manufacture and design-for-test passes, vendor-neutral IPC-2581 / ODB++ / Gerber + IPC-356 netlist hand-off.
Pre-compliance scans in the lab and at the chamber, conducted and radiated emissions, ESD / EFT / surge resilience. Design-stage filter and layout choices that get a board through FCC Part 15 (Class B / Class A), CE EN 55032 / EN 55035, and the IEC 61000-4 transient suite — not after-the-fact ferrite-bead remediation.
Stack-up planning, decoupling network design, PDN target-impedance budgets, TDR-validated transmission lines, VNA-measured impedance on the controlled-Z layers. Power rails sequenced and characterized at every load step before firmware bring-up starts.
IR thermography on every bring-up, junction-to-ambient budgets against the BoM's package thermals, heatsink and airflow design where the margin is tight. ANSYS Icepak or Siemens FloEFD conjugate heat-transfer modelling for forced-air and free-convection enclosures.
How we engage
We organize every hardware program around the same five-step flow so you always know where the work is, what the next gate is, and what the deliverable looks like at each stage.
Block diagram, BoM cost target, regulatory scope, environmental envelope, test-plan outline. The artifact: a written requirements doc the schematic will be reviewed against.
Component selection against second-source and lifecycle constraints, SPICE simulation on the non-trivial loops, design reviews. The artifact: a schematic + BoM that meets every requirement in the doc above.
Stack-up + impedance budgets, placement + routing, signal- and power-integrity checks, DFM / DFT pass with the chosen CM. The artifact: IPC-2581 / ODB++ / Gerber + drill + IPC-356 netlist, ready for fabrication.
First-article assembly review, power-up under current limit, rail sequencing, firmware bring-up, EMC pre-compliance scan, thermal IR pass. The artifact: a bring-up report against the test plan, with every checkbox green or with a written disposition.
DFM-cleaned files, panelization, ICT / AOI / flying-probe fixture design, supplier qualification, first-production-lot review, ongoing yield support. The artifact: a production package the CM can build to with no engineering-side questions left open.
The bench
Every project uses the right tool for the job, but the deliverable is always portable: ODB++ / IPC-2581 / Gerber + a written test plan, not a proprietary database the next engineer can't open. If your team prefers KiCad, we ship in KiCad. If your CM expects Altium, we ship in Altium. The output is what's portable; the choice of input tool is what's pragmatic.
What we deliver
Every program closes with the same artifact list — files in vendor-neutral formats, a written test plan with results, and a DFM-clean production package the CM can build to without an engineering escalation.
Why A1SI
Every board is engineered against a written test plan before the first prototype is ordered, and every test on that plan is run against the first article. If a test fails, the disposition is written into the report — accept, rework, redesign — and the design loop closes against the disposition. We do not ship designs that fail their own qualification suite.
A1SI's predecessor companies have been shipping production-floor hardware controllers since 1992 — the Ford FN-145 seat testers, the DVP2 digital multi-printer, the Spartan ActiveRide suspension controller, the GM ATEC EPROM programmer. Lessons from the line — operator-readable diagnostics, savable serial logs, openly-documented interfaces — shape every board we touch.
ODB++ / IPC-2581 / Gerber + IPC-356 netlist + IPC-A-610 acceptance criteria + a written bring-up report. Your CM gets every artifact in a vendor-neutral format; your next engineer gets a design they can open in the toolchain of their choosing. No lock-in to a proprietary file format, no NDA-only IP, no "trust us, it works."
A1SI picks up programs at every stage — concept, schematic, layout, bring-up, EMC pre-compliance, production hand-off, second source, end-of-life redesign. Send the block diagram, the regulatory target, or the bring-up report you're stuck on; we'll come back with what we'd do next and what the engagement would look like.
"Altium" and "Altium Designer" are trademarks of Altium Limited. "KiCad" is a trademark of the KiCad project under the CERN Open Hardware License umbrella. "LTspice" is a trademark associated with Linear Technology Corporation / Analog Devices, Inc. "PSpice" is a trademark of Cadence Design Systems, Inc. "Keysight", "ADS", and "HFSS" are trademarks of Keysight Technologies, Inc. / Ansys, Inc. (HFSS is now an Ansys product). "ANSYS" and "Icepak" are trademarks of Ansys, Inc. "Siemens" and "FloEFD" are trademarks of Siemens AG / Mentor Graphics Corporation. "Tektronix" is a trademark of Tektronix, Inc. "Saleae" is a trademark of Saleae, Inc. "Rigol" is a trademark of Rigol Technologies, Inc. "FCC" refers to the United States Federal Communications Commission. "CE" refers to the European Conformité Européenne marking. "IPC" refers to IPC International, Inc.; standards cited (IPC-2581, IPC-A-610, IPC-7711/7721, IPC-356) are published by IPC International, Inc. "ODB++" is a trademark of Mentor Graphics Corporation / Siemens. "Ford", "Mustang", and "FN-145" are trademarks of Ford Motor Company. "LUCHT" and "DVP2" are trademarks associated with Lucht Engineering Inc. "Spartan Motors" and "SmartRide" are trademarks associated with Spartan Motors Chassis Inc. / The Shyft Group. Descriptive editorial use only; A1SI is not affiliated with or endorsed by any named third party.